Relating to designing the wiring path between a bonding pad of a semiconductor chip and a pin of a semiconductor package, the technology of designing the wiring for connection of a plurality of endpoints on a plane through a path passing an area other than a wiring prohibited area on the plane is known. The technology is to generate a side for monitoring temporary wiring density (monitor side) between any of the endpoints and any wiring prohibited area on the plane, and to design a wiring path for connection of endpoints based on the width of the wiring crossing each of the monitor sides.
Also known is the technology of automatically generating a multi-terminal network in a package such as a semiconductor chip etc. to automatically generate a traversable multi-terminal network which can be wired and does not include a redundant path. In this technology, (N−1) terminal wiring data satisfying a provided design rule for a package is provided as initial data so that an N terminal (N is an integer equal to or larger than 3) network can be automatically generated. In this technology, based on the terminal group at the wiring start point and the terminal group at the N-th terminal for which a net is to be generated, the interposed terminal group is ignored in performing a 2-terminal net generating process. Then, a provisional net is generated by combining the initial data and an execution result of the 2-terminal net generating process, and the provisional net is amended to satisfy the design rule of a package.
Further known is the technology of automatically determining by the operating process the position of the optimum wiring to each via portion which is wired from each pad portion on the board. In this technology, the distance between the intersection formed by two temporary wiring connecting each pad portion and each via portion and each of the corresponding via portions is determined. The temporary wiring indicating a longer distance is bypassed round the via portion corresponding to the temporary wiring indicating a shorter distance, thereby determining provisional wiring. This process is sequentially performed on all intersections formed by each temporary wiring. Next, the distance between the intersection of two provisional wiring or of provisional wiring and temporary wiring and a corresponding via portion of the provisional wiring or the temporary wiring is determined. The provisional wiring or the temporary wiring indicating the longer distance is bypassed round the corresponding via portion of the provisional wiring or temporary wiring indicating the shorter distance, thereby determining the optimum wiring. This process is sequentially performed on all intersections formed by the provisional wiring and by provisional wiring and temporary wiring.
There is also the well-known technology of setting an optical path set between two nodes as logically as possible in an optical communication network in which a number of nodes are connected by wavelength-multiplexed optical transmission line, thereby reducing the number of wavelengths required in an optical path network. In this technology, the shortest path is searched for by calculating the distance (number of accommodated paths) of the optical transmission line by assuming the faults of all optical transmission lines in a path search for a preliminary path, thereby reducing the wavelengths for the optical transmission line having the largest number of multiplexed wavelengths.
Also known is the technology of appropriately supporting the generation of a wiring path in an integrated circuit package. In this technology, at least each pin, each point between horizontal pins, each point between vertical pins, and each point between diagonal pins of the integrated circuit package are defined as bottleneck portions of wiring, and each bottleneck point is assigned a wiring capacity. Next, two nodes, that is, an inlet node and an outlet node, are generated for each bottleneck. Then, a directional branch from the inlet node in the bottleneck portion to the outlet node is generated for each bottleneck portion. Between adjacent bottleneck portions, a directional branch from one outlet node to another inlet node is generated. Between the bottleneck portion between the diagonal pins and all diagonally adjacent bottleneck portions between the diagonal pins, directional branches from one outlet node to the other inlet node are mutually generated. Then, all generated directional branches are assigned the minimum value of the wiring capacity allocated to the bottleneck portions as the amount of branch capacity.
The technologies described in the following documents are well known.
Document 1:
    Japanese Patent No. 3184796Document 2:    Japanese Patent No. 3548070Document 3:    Japanese Patent No. 4443450Document 4:    Japanese Patent No. 3224114Document 5:    Japanese Laid-open Patent Publication No. 2010-211753
Recently, a printed circuit board for use in electronic equipment indicates an increasing number of wiring sections with the growth of a larger and high-density electronic circuit. Additionally, with an increasing demand for the quality of a waveform accompanied with a higher-speed and power-saving digital signal, there are increasing opportunities of inserting a damping resistor and a terminal resistor especially as a countermeasure against reflective noise. Since preferable effects of these resistor parts cannot be expected unless the shortest possible wire length is realized for a connection by an arrangement in an appropriate position, a designer of a printed circuit board arranges resistor parts and performs a wiring designing operation between terminals (pins) by careful consideration for shorter wiring.
For example, when a part provided with a large number of pins such as a BGA (ball grid array) etc. (hereafter referred to as a “multi-pin part”) is arranged, it is necessary to arrange several tens to several hundreds of resistor parts around the part (multi-pin part), and design the wiring by consideration for shorter wiring. In a general method to realize the wiring with a single layer, the wiring is first devised to make the least possible bypass from each pin in the multi-pin part to the outside of the multi-pin part. Next, depending on the wiring order, the resistor parts such as a chip resistor, a multiple-stage resistor, etc. are arranged, or the resistor parts are replaced, thereby performing a connection to the above-mentioned wiring. However, with a larger number of wiring sections, a previously mounted wiring line may often become an interference with a subsequently mounted wiring line, and an amendment to a wiring path is to be made for each interference. The amendment is a factor of taking a long time in the wiring design for a printed circuit board.